Static Verification

What Does Static Verification Mean?

Static verification is an analysis of computer code to ensure that standard coding practices have been adhered to without having to run the program. An analysis is performed on some versions of the source code and provides a way for programmers to debug new code and detect potential errors in compiled code.


Techopedia Explains Static Verification

Static verification is widely used in software for safety-critical computer systems. The key technologies used in static verification are static timing analysis and equivalence checking. Timing and functional verification in a static verification flow are separated and run in parallel. Static timing analysis provides timing checks, while equivalence checking verifies the functional equivalence of two versions of the same circuit as design scales through different transformations such as scan chain reordering, routing and placement.

A few implementation techniques of static verification are data flow analysis, model checking, abstraction interpretation and assertion usage.

Tools generally used for static verification include Sonar, Yasca, Copy/paste detector, Stylecop, FxCop, BLAST, Clang, Lint and Checkstyle.


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