Pipeline Burst Cache

What Does Pipeline Burst Cache Mean?

Pipeline burst cache (PBC) is a type of cache module or memory that enables a processor in reading and fetching data in succession from a data pipeline.


It is a cache memory architecture that is used for designing L1 and L2 caches. It was first unveiled in the mid-1990s as an alternative to the asynchronous cache or synchronous burst cache.

Techopedia Explains Pipeline Burst Cache

Pipeline burst cache (PBC) primarily is designed to increase the cache memory operations and minimize processor wait time. Generally, PBC (usually L1 or L2 cache) is directly attached or connected to the processor as a data storage or buffer.

The data from PBC are retrieved or written in a succession of four cycles – it requires four successive transfers before the storage from cache is transferred to the processor.

Pipeline burst cache works on two different modes:

  1. Burst Mode: Allows the cache to pre-fetch memory contents before they are required by the processor.
  2. Pipelining Mode: In this mode, similar memory value can be accessed from the cache and RAM simultaneously.

With PBC, the data to be processed next by the processor are pre-held in a buffer or storage area.


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Margaret Rouse

Margaret Rouse is an award-winning technical writer and teacher known for her ability to explain complex technical subjects to a non-technical, business audience. Over the past twenty years her explanations have appeared on TechTarget websites and she's been cited as an authority in articles by the New York Times, Time Magazine, USA Today, ZDNet, PC Magazine and Discovery Magazine.Margaret's idea of a fun day is helping IT and business professionals learn to speak each other’s highly specialized languages. If you have a suggestion for a new definition or how to improve a technical explanation, please email Margaret or contact her…