A SerDes chip facilitates the transmission between two points that use parallel data over serial streams, reducing the number of data paths required for the transmission. This lowers the number of required connecting pins, so wires and connectors can be kept small and thin. On the transmitter side, parallel data are converted to serial data, whereas on the receiver side the opposite happens. Most SerDes devices are fully capable of full-duplex operation, so conversion of data takes place in both directions simultaneously. SerDes chips are used in wireless routers, gigabit Ethernet systems, storage applications and fiber optic communication systems.

The basic SerDes function has two blocks: the Parallel In Serial Out (PISO) block or parallel-to-serial converter, and the Serial In Parallel Out (SIPO) block or serial-to-parallel converter. Each end of a communication link has a SerDes with these two fundamental blocks; the PISO block is used for transmission and the SIPO block is used for reception.

SerDes chips are available in several architectures:

• Parallel clock — This is used to serialize a parallel bus input together with data addresses and control signals. A reference clock is used to synchronize the data stream, which has a jitter tolerance at the serializer of 5–10 ps rms.
• Embedded clock — This serializes the data and the clock into a single stream. One clock cycle is transmitted first followed by the actual data, creating a periodic rising edge at the beginning of the data stream.
• 8b/10b SerDes — This maps the data to a 10-bit code right before serializing. The deserializer makes use of the reference clock to monitor the recovered clock from the bit stream.
• Bit interleaved — This multiplexes multiple slower serial data streams into faster streams, whereas the receiver demultiplexes the faster streams back into multiple slower streams.