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Dynamic Random Access Memory (DRAM)

Definition - What does Dynamic Random Access Memory (DRAM) mean?

Dynamic random access memory (DRAM) is a type of random-access memory used in computing devices (primarily PCs). DRAM stores each bit of data in a separate passive electronic component that is inside an integrated circuit board. Each electrical component has two states of value in one bit called 0 and 1. This captivator needs to be refreshed often otherwise information fades. DRAM has one capacitor and one transistor per bit as opposed to static random access memory (SRAM) that requires 6 transistors. The capacitors and transistors that are used are exceptionally small. There are millions of capacitors and transistors that fit on one single memory chip.

Techopedia explains Dynamic Random Access Memory (DRAM)

DRAM is dynamic memory and SRAM is static memory. The DRAM chips on a circuit board need to refresh every few milliseconds. This is done by rewriting the data to the module. Chips that need refreshing are volatile memory. DRAM accesses the memory directly, holds memory for a short period and loses its data when the power is shut off. SRAM is volatile memory that is static and does not need refreshing. Because SRAM is a lot faster, it is used in registers and cache memory. SRAM keeps data and performs at higher speeds than DRAM. Although SRAM is faster, DRAM is used more often on the motherboard because it is a lot cheaper to manufacture.

The three main types of circuit boards that contain memory chips are dual in-line memory modules (DIMMs), single in-line memory modules (SIMMs) and Rambus in-line memory modules (RIMM’s). Today the majority of motherboards use DIMMs. The module refresh rate for DRAM is every few milliseconds (1/1000th of a second). This refreshing is done by the memory controller located on the chipset of the motherboard. Because refresh logic is used for automatic refresh, a DRAM circuit board is quite complex. There are different systems used for refreshing but all methods require a counter to keep track of the row that needs to be refreshed next. The DRAM cells are organized in a square collection of capacitors, typically 1024 by 1024 cells. When a cell is in the “read” state, an entire row is read out and the refresh is written back. When in a “write” state, a whole row is “read” out, one value is changed, and then the whole row is rewritten. Depending on the system, there are DRAM chips that contain a counter while others systems rely on a peripheral refresh logic which includes a counter. DRAM’s access time is around 60 nanoseconds, while SRAM can be as low as 10 nanoseconds. As well, DRAM’s cycle time is a lot longer than SRAM’s. The cycle time of SRAM is shorter because it does not need to stop between accesses and refreshes.

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