Backside Bus

What Does Backside Bus Mean?

A backside bus (BSB) is an internal bus that connects the central processing unit to the cache memory, such as Level 2 (L2) and Level 3 (L3) cache. The CPU often stores memory in the cache. Here it stores data that is frequently used and needs to be promptly retrieved.


Prior to the BSB, computers used the single bus system, which was much slower and often created bottlenecks. The BSB improved CPU communication with cache memory by reducing general signals and eliminating excess procedures. Today, most PCs integrate L2 and L3 cache into the CPU, making BSB obsolete.

Techopedia Explains Backside Bus

There are two internal buses that carry data to and fro from the CPU: the backside bus and the frontside bus (FSB). The backside bus transmits data between the CPU and the secondary cache, while the frontside bus communicates between the CPU and the memory. The CPU needs to quickly access L2 cache when needed. If L2 cache memory cannot be quickly located and transmitted, the CPU will be less efficient.

The L2 cache is located near the CPU so it can be easily accessed. The secondary cache stores data that is repeatedly used so that it can be swiftly transmitted to assist the CPU in processing data more efficiently. Often the BSB has a clock speed near the speed of a processor. The FSB, on the other hand, is much slower at around half the processor speed.

Before a CPU reads or writes data to the main memory, it first examines the data in cache to see if there is a copy. If there is a copy of the data, the CPU promptly reads or writes from the cache, which drastically speeds up processing.

In older PCs, there was no L2 or L3 cache. Instead, the backside bus accessed cache externally, which was slow, but still much faster than using RAM through the FSB. A system that uses both buses is called a dual-bus architecture or dual independent bus (DIB) architecture. A computer that has DIB architecture has one bus that connects to the main memory and another bus that connects to the L2 cache. The dual-bus architecture introduced many new designs. Today, most PCs have integrated L2 and L3 cache on the CPU, which has made the BSB obsolete.


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Margaret Rouse

Margaret Rouse is an award-winning technical writer and teacher known for her ability to explain complex technical subjects to a non-technical, business audience. Over the past twenty years her explanations have appeared on TechTarget websites and she's been cited as an authority in articles by the New York Times, Time Magazine, USA Today, ZDNet, PC Magazine and Discovery Magazine.Margaret's idea of a fun day is helping IT and business professionals learn to speak each other’s highly specialized languages. If you have a suggestion for a new definition or how to improve a technical explanation, please email Margaret or contact her…