Bus mastering allows a control bus to access RAM independently from the CPU. It is designed to allow data transfer between a peripheral component and RAM while the CPU implements other responsibilities.

The bus master platform is most commonly found in distinct input/output (I/O) devices or in a microprocessor. It directs traffic on an I/O pathway or computer bus. The bus master is the “master” and controls the bus pathways that contain the transmission signals and address. The input and output (I/O) devices on a bus are the “slaves”.

If a computer contains several components that support bus mastering, hierarchical structure needs to be implemented to prevent several components from trying to use the bus at the same time. There are several structures such as:

• Small Computer System Interface (SCSI): Transfers data between the computer and peripheral devices. Includes a permanent priority for each SCSI ID
• Serial Peripheral Interface (SPI): Operates in full duplex mode (both directions) using master/slave architecture. The master device initiates the data frame, which includes frame synchronization.
• Inter-Integrated Circuit (I²C) Interface: Has a bidirectional serial bus architecture that contains stop and start bit messages, which control data transfer.