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Double data rate (DDR) is the advanced version of synchronous dynamic random access memory (SDRAM). SDRAM waits for clock signals before responding to control inputs. DDR uses both the falling and rising edges of the clock signal. The difference between SDRAM and DDR is not the speed, but rather how many times data is transmitted with each cycle. DDR transfers data twice per clock cycle, whereas SDRAM sends signals once per clock cycle. The same frequencies are used for both. However, DDR uses both edges of the clock, whereas SDRAM uses only one. DDR is outdated but is still in use, such as for the output of analog-to-digital converters. Updated DDR versions are DDR2 and DDR3.
DDR is also known as dual pumped rate, double pumped rate or double transition rate.
DDR is used in conjunction with microprocessors to carry data between the central processing unit (CPU) and the north bridge, which is one of the two chips in the core logic chipset. This pathway is called the front-side bus. DDR is also used for DDR SDRAM, Ultra-3 SCSI, accelerated graphics ports and the HyperTransport bus on AMD’s Athlon 64 processors. DDR has a memory clock speed of at least 200MHz. The DDR quickly became quite popular because it was cheaper, offered double the transfer rate and consumed less power than older SDRAM modules, which expended 3.3 volts compared to DDR's 2.6 volts. DDR also produces less heat than SDRAM. SDRAM became obsolete as new standards for DDR synchronous DRAMs, as well as several other DDR-based memory modules, were developed by the Joint Electron Devices Engineering Council (JEDEC) Solid State Technology Association.
The DDR module uses a 184-pin connector. Both DDR and the newer DDR2 use a 64-bit-wide data bus. DDR2 and DDR3 use 240-pin dual inline memory modules. To ensure the right module is inserted on the motherboard correctly, DDR, DDR2 and DDR3 modules are all keyed differently. Improving on DDR’s double pumping, there are new modules with quad pumping. Quad data rate pumping transmits data at four points in the clock cycle. This module delivers four bits of data per signal line per clock cycle. Quad pumping operates at twice the frequency of the clock signal, while DDR operates at the same frequency.