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Extended data out random access memory (EDO RAM/DRAM) is an early type of dynamic random access memory (DRAM) chip which was designed to improve the performance of fast page mode DRAM (FPM DRAM) that was used in the 1990s. Its main feature was that it eliminated wait times by allowing a new cycle to start while retaining the data output buffer from the previous cycle active, which allows a degree of pipelining (overlap in operation) that improved performance.
Techopedia Explains Extended Data Out Random Access Memory
Extended data out dynamic random access memory was introduced in 1994 and began to replace fast page mode DRAM by 1995 when Intel first introduced the 430FX chipset that supports EDO DRAM. Before that, EDO DRAM could replace FPM DRAM, but if the memory controller was not specifically designed for the EDO, then the performance remained the same as FPM.
Single-cycle EDO DRAM is able to carry out an entire memory transaction in a single clock cycle, otherwise, it can do it in two cycles instead of three, once the page has been selected. The EDO’s capability allowed it to replace the slow L2 cache of PCs at that time and reduced the huge performance loss associated with the L2 cache, while making PCs cheaper to build overall. So a system using EDO with L2 cache was much faster compared to the FPM and L2 cache combination, while also being cheaper to build.
EDO was rated for 40 MHz maximum clock rate, 64 bits of bus bandwidth, 320 MBps peak bandwidth and ran at 5 volts. It was tangibly faster than the older FPM DRAM that had only 25 MHz max clock rate and 200 MBps peak bandwidth. However, it was superseded by the faster SDRAM starting in 1996, after only two years of major use.
